The present inventive concepts relate to clock gating, and more particularly to an integrated clock gater (ICG) circuit using complimentary switch logic having high performance and low power consumption characteristics.
Mobile devices are becoming ubiquitous. Such devices include smart phones, tablets, personal digital assistants (PDAs), notebook computers, and the like. Digital processors are used in such devices for executing logical instructions. The digital processors operate in response to one or more clock signals. With each pulse of the clock signal, one or more logical instructions can be executed or partially executed by the processor. In this manner, the mobile devices can perform functions that have become integral and useful to the personal lives of millions of people.
Typically, clock elements within the processor tend to consume relatively large amounts of power due to high frequency activity. To avoid power waste, techniques have been developed to limit high frequency clock activity. Quite often, one or more state machines or sequential elements within the processor are dormant while waiting for other events to occur. The high frequency clock signal fed to these elements can be “gated” by clock gating, which sets the gated clock to a quiescent state.
Clock gating is a power mitigation technique that can be accomplished using specially designed clock gating cells. When the clock gating cell is enabled, the clock signal is passed from its input clock pin to its output—the enabled clock pin. When the clock gating cell is gated, the output clock signal is held in its quiescent state, which is typically a logical value of zero for positive edge-triggered state elements.
FIG. 1 is an example of a conventional clock gating circuit referred to as an enable pre-latched on clock low integrated clock gater circuit, also sometimes referred to as a PREICG circuit. The PREICG circuit includes an AND gate 125 and a latch 120. The AND gate 125 receives a clock signal CLK 105 and an enable signal EN 115. The latch 120 latches the enable signal 115 while CLK 105 is at a logic level 0 state. The enable signal 115 is considered to be latched once CLK 105 transitions to a logic level 1 state. The output of latch 120 is EN_LAT 130. The value of EN_LAT 130 does not change while CLK 105 is in a logical 1 state. When the EN_LAT 130 signal is asserted, the clock signal CLK 105 is passed through the AND gate 125, such that GATED CLK 110 is now an active clock signal. On the other hand, when the EN_LAT 130 signal is not asserted, the clock signal CLK 105 is not passed through the AND gate 125, but instead, the gated clock signal GATED CLK 110 is quiescent.
Some of the disadvantages of the PREICG clock gating circuit include large enable setup requirements and high latency (i.e., insertion delay), which can impact clock uncertainty and can also decrease the maximum possible frequency. In addition, combined with complex combinations of clock gating, the enable signal can have very little arrival slack. Moreover, the PREICG clock gating circuit degrades the maximum frequency to about 1 GHz due to high enable setup and insertion times.
Another conventional approach is shown in FIG. 2. This type of clock gating circuit is referred to as a pulse-based integrated clock gater (PICG) circuit. The PICG circuit creates an internal pulse that is smaller than the regular clock signal. The internal pulse can have a frequency that is twice that of the regular clock signal. In a critical path within certain circuitry of the processor, the performance can be doubled for a period of time, and then at some point later, the performance is returned to the normal mode.
As can be seen in FIG. 2, the PICG circuit includes a pulse circuit 245, a latch 220, an inverter 250 and other control elements such as transistors P1, N1 and N2. The pulse circuit 245 includes a delay circuit 240, a NAND gate 225, and an inverter 230. The width of the internal pulse is defined by the amount of delay introduced by the delay circuit 240. The NAND gate 225 receives the clock signal CLK 205 and the delayed clock signal, and from these signals, produces a pulsed clock signal CLK 235. The pulsed clock signal CLK 235 controls whether or not the control transistor N2 is turned on or off. An enable signal 215 controls whether or not the transistor N1 is turned on or off. The regular clock signal CLK 205 controls whether or not the transistor P1 is turned on or off.
When the enable signal 215 is not asserted, the transistor N1 remains turned off, which causes the latch 220 to latch the voltage potential of node ‘A’ to a high level (e.g., VDD), despite the ongoing oscillations of the clock signal CLK 205. The inverter 250 inverts this high level to a low level, which results in the GATED CLK 210 being set to a quiescent state. Conversely, when the enable signal 215 is asserted, the transistor N1 is turned on, which causes the flow of electrical current from node ‘A’ to GND to be dependent on transistors N2 and P1. In other words, in this state, node ‘A’ swings between VDD and GND at the frequency of the pulsed clock signal CLK 235. As a result, the gated clock signal CLK 210 swings between VDD and GND at the frequency of the pulsed clock signal CLK 235, although at an opposite polarity due to the inverter 250.
One of the benefits of the PICG design is that they have a small setup time. In other words, the enable signal EN 215 can arrive close to the rising edge of the clock signal CLK 205. This provides additional cycle time to meet timing on critical paths. However, this comes at the expense of high power usage because the pulse circuit 245 consumes significant power and is always on. In other words, the pulse circuit 245 itself is never clock gated, but rather, it continually consumes energy. The PICG circuit power usage is 1.5 times that of the PREICG circuit when the clock is enabled, and up to 10 times the power usage of the PREICG circuit when the clock is in a disabled mode. Consequently, even if the enable signal EN 215 is not asserted, the PICG circuit is always consuming clock power.
What is needed is an integrated clock gater (ICG) circuit that delivers high performance and low power consumption. It would also be desirable to provide an ICG circuit having a small enable setup time and a small clock-to-enabled-clock delay. The inventive concepts disclosed herein implement clocked complimentary voltage switched logic within an ICG circuit (generally referred to herein as a CICG circuit), thereby delivering a significant reduction in clock power consumption in the enabled mode, and a particularly significant reduction in power when in the disabled mode. Together with related inventive concepts disclosed herein, these and other limitations in the prior art are addressed.